Accellera Announces IEEE 1800™-2023 Standard Available Through IEEE GET Program
March 04, 2024 12:30 ET
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Accellera Systems Initiative
Accellera Announces IEEE 1800™-2023 Standard Available Through IEEE GET Program
Real Intent Provides Comprehensive Reset Analysis with Meridian RXV
October 29, 2018 08:00 ET
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Real Intent
New Tool Offers Reset Audit, Reset Optimization and RTL X-Optimism Analysis SUNNYVALE, Calif., Oct. 29, 2018 (GLOBE NEWSWIRE) -- Real Intent, Inc., a leading provider of SoC and FPGA sign-off...
Open-Silicon Appoints New VP of Engineering
September 18, 2018 08:00 ET
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Open-Silicon
MILPITAS, Calif., Sept. 18, 2018 (GLOBE NEWSWIRE) -- Amid rapid custom silicon growth and innovation, Open-Silicon today announced the appointment of semiconductor industry veteran Anand Bariya as...
Real Intent to Exhibit New Products at the 55th DAC in San Francisco
June 19, 2018 08:00 ET
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Real Intent, Inc.
SUNNYVALE, Calif., June 19, 2018 (GLOBE NEWSWIRE) -- What:Real Intent will showcase its new Verix family of products including the just announced PhyCDC product for gate-level CDC sign-off and...
Real Intent Launches Verix PhyCDC – the Next Innovation in SoC Design Sign-off
June 18, 2018 08:00 ET
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Real Intent, Inc.
SUNNYVALE, Calif., June 18, 2018 (GLOBE NEWSWIRE) -- Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced Verix PhyCDC – a new tool to debug clock...
Real Intent's New Verix SimFix Software Delivers First Intent-Driven Remedy for Verification Pessimism
May 30, 2018 08:00 ET
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Real Intent, Inc.
SUNNYVALE, Calif., May 30, 2018 (GLOBE NEWSWIRE) -- Real Intent, a leading provider of SoC and FPGA sign-off verification solutions, today launched Verix SimFix, the first intent-driven verification...
Sidense SHF Embedded Memory Macros Target High-Performance and Low-Power Applications in TSMC 28nm Processes
May 29, 2014 09:00 ET
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Sidense
OTTAWA, ON--(Marketwired - May 29, 2014) - Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that the Company's 1T-OTP macros for TSMC's 28nm HPL, HPM and HPC...
eSilicon Engineers' Comprehensive Book on Low-Power Design for ASICs Is Now Available
February 05, 2013 08:00 ET
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eSilicon
SUNNYVALE, CA--(Marketwire - Feb 5, 2013) - eSilicon Corporation, the largest independent semiconductor design and manufacturing services provider, today announced that An ASIC Low-Power Primer is...